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HIP1011B
Data Sheet March 2000 File Number 4640.3
PCI Hot Plug Controller
The HIP1011B, the third product in the HIP1011 family, is an electronic circuit breaker that monitors, reports and protects circuits from excessive load currents. As a pin-for-pin drop-in alternative offering similar functionality to the widely used HIP1011, the HIP1011B is compatible with CompactPCI peripheral boards and PCI Hot Plug systems where voltage "health" monitoring and reporting are centralized by the system controller IC. The HIP1011B does not monitor nor respond to under voltage conditions thus making control of a wide range of voltages possible. The HIP1011B creates a small and simple yet complete power control solution to control the four independent supplies (+5V, +3.3V, +12V, and -12V) found in PCI and CompactPCI systems. For the +12V and -12V supplies, overcurrent protection is provided internally with integrated current sensing FET switches. For the +5V and +3.3V supplies, overcurrent protection is provided by sensing the voltage across the external current-sense resistors. The PWRON input controls the state of both internal and external switches. During an overcurrent condition on any output, all MOSFETs are latched-off and a LOW (0V) is asserted on the FLTN output. The FLTN latch is cleared when the PWRON input is toggled low again. During initial power-up of the main VCC supply (+12V), the PWRON input is inhibited from turning on the switches, and the latch is held in the Reset state until the VCC input is greater than 10V. User programmability of the overcurrent threshold, response time and turn-on slew rate is provided. A resistor connected to the OCSET pin programs the overcurrent thresholds. A capacitor may be added to the FLTN pin to adjust the fault reporting and power-supply latch-off response times after an over-current event. Capacitors connected to the gate pins determine the turn-on rate.
Features
* Allows for System Centralized Voltage Monitoring * Adjustable Delay to Fault Notification and Latch-Off * Controls Four Supplies: +5V, +3.3V, +12V, and -12V * Internal MOSFET Switches for +12V and -12V Outputs * P Interface for On/Off Control and Fault Reporting * Adjustable Overcurrent Protection for All Supplies * Provides Overcurrent Fault Isolation * Adjustable Turn-On Slew Rate * Minimum Parts Count Solution * No Charge Pump
Applications
* PCI Hot Plug * CompactPCI
Pinout
HIP1011B (SOIC) TOP VIEW
M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET 1 2 3 4 5 6 7 8 16 M12VO 15 M12VG 14 12VG 13 GND 12 12VO 11 5VISEN 10 5VS 9 PWRON
Ordering Information
PART NUMBER HIP1011BCB HIP1011BCB-T TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 16 Ld SOIC Tape and Reel PKG. NO. M16.15
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 2000
HIP1011B Typical Application
3.3V INPUT 3.3V, 7.6A OUT 5m, 1% 12V, 0.5A OUT -12V, 0.1A OUT 5V, 5A OUT 5m, 1% 5V INPUT
HUF761315K8 -12V INPUT HIP1011B M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET M12VO M12VG 12VG GND 12VO 5VISEN 5VS PWRON 0.033F 0.033F 0.033F
12V INPUT
6.04k 1% POWER CONTROL INPUT FAULT OUTPUT (ACTIVE LOW)
(OPTIONAL)
NOTE: ALL CAPACITORS ARE 10%.
Simplified Schematic
VCC SET (LOW = FAULT) FAULT LATCH LOW = FAULT FLTN
VCC +
-
VCC
RESET COMP +
VOCSET/17
-
5VS VCC 3V5VG
VCC 5VREF 5V ZENER REFERENCE 5VISEN VOCSET/13.3 VCC 12VIN POWER-ON RESET VCC LOW WHEN VCC < 10V COMP VOCSET/0.8 + 12VIN 0.3 VCC 12VG 100A VOCSET OCSET VCC PWRON + COMP VOCSET/3.3 + M12VO HIGH = FAULT HIGH = SWITCHES ON COMP + +
-
3VS
-
3VISEN
+
-
GND
2
-
-
12VO
M12VG
0.7 M12VIN
HIP1011B Pin Descriptions
PIN 1 2 3 4 5 6 7 8 DESIGNATOR M12VIN FLTN 3V5VG VCC 12VIN 3VISEN 3VS OCSET FUNCTION -12V Input Fault Output 3.3V/5V Gate Output 12V VCC Input 12V Input 3.3V Current Sense 3.3V Source Overcurrent Set DESCRIPTION -12V Supply Input. Also provides power to the -12V overcurrent circuitry. 5V CMOS Fault Output; LOW = FAULT. A capacitor may be placed from this pin to ground to provide delay time to fault notification and power supply latch-off. Drive the Gates of the 3.3V and 5V MOSFETs. Connect a capacitor to ground to set the startup ramp. During turn on, this capacitor is charged with a 25A current source. Connect to unswitched 12V supply. Switched 12V supply input. Connect to the load side of the current sense resistor in series with source of external 3.3V MOSFET. This pin tied to GND when FET switch outputs disabled. Connect to Source of 3.3V MOSFET. This connection along with pin 6 (3VISEN) senses the voltage drop across the sense resistor. Connect a resistor from this pin to ground to set the overcurrent trip point of all four switches. All four over current trips can be programmed by changing the value of this resistor. The default (6.04k, 1%) is compatible with the maximum allowable currents as outlined in the PCI specification. Controls all Four Switches. High to Turn Switches ON, Low to turn them OFF. Connect to Source of 5V MOSFET Switch. This connection along with pin 11 (5VISEN) senses the voltage drop across the sense resistor. Connect to the load side of the current sense resistor in series with source of external 5V MOSFET. This pin tied to GND when FET switch outputs disabled. Switched 12V output. This pin tied to GND when FET switch outputs disabled. Connect to common of power supplies. Connect a capacitor between 12VG and 12VO to set the start up ramp for the +12V supply. This capacitor is charged with a 25A current source during start-up. Connect a capacitor between M12VG and M12VO to set the start-up ramp for the M12V supply. This capacitor is charged with 25A during start-up. Switched 12V Output. This pin tied to GND when FET switch outputs disabled.
9 10 11 12 13 14 15 16
PWRON 5VS 5VISEN 12VO GND 12VG M12VG M12VO
Power On Control 5V Source 5V Current Sense Switched 12V Output Ground Gate of Internal PMOS Gate of Internal NMOS Switched -12V Output
3
HIP1011B
Absolute Maximum Ratings
VCC, 12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V 12VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V12VIN + 0.5V 12VO, 12VG, 3V5VG . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15.0V to + 0.5V M12VO, M12VG . . . . . . . . . . . . . . . . . . . . . VM12VIN-0.5V to + 0.5V 3VISEN, 5VISEN . . . . . . . . . . . -0.5V to the lesser of VCC or + 7.0V Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . . . . . . -0.5V to + 7.0V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4KeV (HBM)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 125oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Die Characteristics
Number of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Operating Conditions
VCC Supply Voltage Range. . . . . . . . . . . . . . . . . +10.8V to +13.2V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.5A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.1A Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details. 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER 5V/3.3V SUPPLY CONTROL 5V Overcurrent Threshold 5V Overcurrent Threshold Voltage 5V Overcurrent Threshold Voltage 5V Turn-On Time (PWRON High to 5VOUT = 4.75V) 5VS Input Bias Current 5VISEN Input Bias Current 3V Overcurrent Threshold 3V Overcurrent Threshold Voltage 3V Overcurrent Threshold Voltage 3V Turn-On Time (PWRON High to 3VOUT = 3.00V) 3VS Input Bias Current 3VISEN Input Bias Current 3V5VG VOUT High Gate Output Charge Current Gate Turn-On Time (PWRON High to 3V5VG = 11V) Gate Turn-Off Time Gate Turn-Off Time
Nominal 5V and 3.3V Input Supply Voltages, VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IOC5V VOC5V_1 VOC5V_2 tON5V IB5VS IB5VISEN IOC3V VOC3V_1 VOC3V_2 tON3V IB3VS IB3VISEN
See Figure 1, Typical Application VOCSET = 0.6V VOCSET = 1.2V C3V5VG = 0.022F, C5VOUT = 2000F, RL = 1 PWRON = High PWRON = High See Figure 1, Typical Application VOCSET = 0.6V VOCSET = 1.2V C3V5VG = 0.022F, C3VOUT = 2000F, RL = 0.43 PWRON = High PWRON = High
30 66 -
8 36 72 6.5
42 79 -
A mV mV ms A A A
-40 -160
-26 -140 10
-20 -110
42 88 -
49 95 6.5
56 102 -
mV mV ms A A V A s s s
-40 -160 11 22.5 -
-26 -140 11.7 25.0 280
-20 -110 27.5 500
VOUT_HI_35VG 3V5VG IOUT = 5 IC3V5VG tON3V5V tOFF3V5V PWRON = High, V3V5VG = 2V C3V5VG = 0.1F C3V5VG = 0.1F, 3V5VG from 9.5V to 1V C3V5VG = 0.022F, 3V5VG Falling 90% to 10%
-
13 2
17 -
4
HIP1011B
Electrical Specifications
PARAMETER +12V SUPPLY CONTROL On Resistance of Internal PMOS Overcurrent Threshold Overcurrent Threshold Gate Charge Current Turn-On Time (PWRON High to 12VG = 1V) Turn-Off Time Turn-Off Time -12V SUPPLY CONTROL On Resistance of Internal NMOS Overcurrent Threshold Overcurrent Threshold Gate Output Charge Current Turn-On Time (PWRON High to M12VG = -1V) Turn-On Time (PWRON High to M12VO = -10.8V) Turn-Off Time Turn-Off Time M12VIN Input Bias Current CONTROL I/O PINS Supply Current OCSET Current Overcurrent Fault Response Time PWRON Threshold Voltage FLTN Output Low Voltage FLTN Output High Voltage FLTN Output Latch Threshold 12V Power On Reset Threshold IVCC IOCSET tOC VTHPWRON VFLTN,OL VFLTN,OH VFLTN,TH VPOR,TH VCC Voltage Falling IFLTN = 2mA IFLTN = 0 to -4mA 4 95 0.8 3.9 1.45 8.7 5 100 500 1.6 0.6 4.3 1.8 9.4 5.8 105 960 2.1 0.9 4.9 2.25 9.9 mA A ns V V V V V IBM12VIN rDS(ON)M12 IOC12V_1 IOC12V_2 ICM12VG tONM12V tONM12V tOFFM12V PWRON = High, ID = 0.1A, TA = TJ = 25oC VOCSET = 0.6V VOCSET = 1.2V PWRON = High, V3VG = -4V CM12VG = 0.022F CM12VG = 0.022F, CM12VO = 50F, RL = 120 CM12VG = 0.1F, M12VG CM12VG = 0.022F, M12VG Falling 90% to 10% PWRON = High 0.5 0.15 0.30 22.5 0.7 0.18 0.37 25 160 0.9 0.25 0.50 28.5 300 A A A s ms s s mA rDS(ON)12 IOC12V_1 IOC12V_2 IC12VG tON12V tOFF12V PWRON = High, ID = 0.5A, TA = TJ = 25oC VOCSET = 0.6V VOCSET = 1.2V PWRON = High, V12VG = 3V C12VG = 0.022F C12VG = 0.1F, 12VG C12VG = 0.022F, 12VG Rising 10% - 90% 0.18 0.6 1.25 22.5 0.3 0.75 1.50 25 16 0.35 0.9 1.8 28.5 20 A A A ms s s Nominal 5V and 3.3V Input Supply Voltages, VCC = 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
-
9 3
12 -
-
16
-
-
18 3 2
23 2.6
5
HIP1011B Typical Performance Curves
340 1000 105
PMOS rON + 12 (m)
NMOS -12 rON
NMOS rON -12 (m)
320
900
95 OC VTH (mV)
3V OCVTH
300 PMOS +12 rON 280
800
85 5V OCVTH 75
700
260 0
600 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
65 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
FIGURE 1. rON vs TEMPERATURE
FIGURE 2. OC VTH vs TEMPERATURE (VROCSET = 1.21V)
102
9.5
101 VPOR VTH (V) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC) I OCSET (A)
9.4
100
9.3
99
9.2
98
9.1 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
FIGURE 3. OCSET CURRENT vs TEMPERATURE
FIGURE 4. VCC POWER ON RESET VTH vs TEMPERATURE
Adjusting the Fault Reporting and Power Supply Latch-Off Delay Times
Figure 5 illustrates the relationship between the FLTN signal and the gate drive outputs. Duration a, indicates the time between FLTN starting to transition from High to Low, (indicating a fault has occurred) and the start of the gate drive outputs latching off. The latch-off is initiated by the falling FLTN signal reaching the output latch threshold voltage, VFLTN, TH. For additional details and wave forms see HIP1011A Data Sheet FN4631. Table 1 illustrates the effect of the FLTN capacitor on the response times.
TABLE 1. RESPONSE TIME TABLE 0.001F 3V5VG Response a 0.85s 0.1F 37s 10F 3.8ms FIGURE 5. TIMING DIAGRAM
T1 T2
VFLTN,TH
FLTN
a
3V5VG
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HIP1011B Applications
Implementing the HIP1011B in the CompactPCI Hot Swap Application
This application offers to the CompactPCI peripheral board designer programmable Over Current (OC) protection, programmable delays to latch off, and soft start ramp turn on for all four supplies with simultaneous latch off upon OC fault detection. Figure 6 illustrates the HIP1011EVAL2 evaluation board for CompactPCI Hot Swap implementation. The shaded components are the external components necessary to accomplish both controlled power up and turn-on. For minimum PCB area single gate logic can be used. PWRON is being held low. With the logic devices powered the inverter U2 input is pulled high putting a low on the three-state driver U1 input which is passed through to the PWRON pin. Upon complete insertion the shortest length pin, "board present" which is tied to ground on the backplane finally contacts the inverter input. The inverter output pulls high turning on the HIP1011B through U1 thus, the board is fully powered on only upon complete insertion.
Fault Reset
If an overcurrent condition is detected on the board by the HIP1011B the FLTN signal transitions low, once the VFLTN,TH is reached all the switches are simultaneously switched off protecting the system, the board and its components. The system controller is notified of the fault occurrence by the FLTN signal. Reset of the faulted card is accomplished by a positive pulse on the three-state oe input. The pulse puts U1 output into a high Z state allowing R4 to pull the HIP1011B PWRON pin low, resetting the HIP1011B. The HIP1011B switches turn back on when U1 oe input returns to a low state resulting in PWRON going high. The reset pulse can be generated by either the system restart/reset to the master board or from the master system board to any of the peripheral boards in the system.
Insertion Sequence
Because of the staggered pin lengths in the CompactPCI connector, as the board is inserted into the slot, the ground bus plane is connected first via the longest pins referencing the HIP1011B by way of the PWRON, OCSET and GND pins through R4 and R3. Additionally the three-state driver, U1 address line is referenced through R6. Subsequently the medium length pins engage to connect the +3.3V, +5V, +12V, -12V lines to the inputs, activating the HIP1011B, and the 2 logic devices, U1 and U2. At this time the HIP1011B is in control holding off all the MOSFET switches, as
3.3VOUT 3.3V INPUT R2
-12VOUT 5VOUT R1 5V INPUT
Q1, Q2 -12V INPUT HIP1011 M12VO M12VIN FLTN 3V5VG VCC 12VIN 12V INPUT R3 3VISEN 3VS OCSET M12VG 12VG GND 12VO 5VISEN 5VS PWRON U1 R4 FLTN C4 oe R6 U2 R5 C2 C1
Q3, Q4 C3
+12VOUT BOARD PRESENT PIN ON BACKPLANE
PULSE HIGH TO RESET FAULT
FIGURE 6. HIP1011B CompactPCI APPLICATION CIRCUIT NOTES: 3. Each test point (TP) on HIP1011EVAL2 refers to device pin number. 4. SIGNAL_GND, SHIELD_GND and SHORTPIN_GND can be jumpered together for ease of evaluation. 5. HIP1011B devices can be placed into HIP1011EVAL2 board for evaluation or contact INTERSIL for a HIP1011B equipped evaluation board.
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HIP1011B HIP1011 Split Load Application
All of the members of the HIP1011 family, including the HIP1011B, can be used in an application where two electrically isolated loads are to be powered from a common bus. This may occur in a system that has a power management feature controlled by a system controller IC invoking a sleep or standby state. Thus one load can be shut down while maintaining power to a second isolated circuit. The circuit shown in Figure 7 shows the external FETs, and sense resistor configuration for the 3.3V and/or 5V load that has such a requirement. The HIP1011 is represented by pin names in rectangles. Q1 and Q2 are the N-Channel FETs for each load on this rail, these are sized appropriately for each load. R1 and R2 are needed to pull down the supply slot pins or load when slot power is disabled as the load discharge FETs (Q3) on the VISEN pins are no longer attached to the load. When power is turned off to the load these (~100) FETs turn on, thus some low current, (10mA) continues to be drawn from the supply in addition to the sleep load current resulting in a 4oC die temperature rise.
VSUPPLY
HIP1011 High Power Circuit
Instances occur when a noncompliant card is designed for use in a PCI environment. Although the HIP1011 family has proven to be very design flexible, controlling high power +12V supplies requires special attention. This is due to thermal considerations that limit the integrated power device on the +12V supply to about 1.5A. To address this an external add on circuit as shown in Figure 8 enables the designer to add the OC monitoring and control of a high power +12V supply in addition to the 3 other power supplies. The HIP1011 is represented by pin names in rectangles. This circuit primarily requires that an external P-Channel MOSFET be connected in parallel to the internal HIP1011 PMOS device and that the discrete device have a much lower rDS(ON) value than the internal PMOS device in order to carry the majority of the current load. By monitoring the voltage across the sense resistor carrying the combined load current of both the internal and external FETs and by using a comparator with a common mode input voltage range to the positive rail and a low input voltage threshold offset to reduce distribution losses, a high precision OC detector can be designed to control a much higher current load than can be tolerated by the HIP1011. An alternative circuit for moderate current levels where both accuracy and cost are lowered can be accomplished by a single external P-Channel MOSFET in parallel with the internal P-Channel MOSFET. For example, if 2X the OC level is desired a 0.3 rDS(ON) P-Channel MOSFET can be used thus approximately doubling the +12 IOUT before latch-off. IOCTOTAL = IOCINTERNAL (1 + rDS(ON) of internal FET/rDS(ON) of external FET).
12VIN R2 12VG Q1 R1 12VO RSENSE + R3 Q2 FLTN
VS RSENSE VISEN Q3 Q1 TO FULL LOAD R1 PWRON Q2 TO SLEEP LOAD R2 SYSTEM POWER MGT CONTROLLER
3V5VG
FIGURE 7. SPLIT LOAD CIRCUIT
12VIN
-
TO +12V LOAD
FIGURE 8. HIGH POWER +12V CIRCUIT
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HIP1011B Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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